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Application Note 9836
Printed Circuit Board
The practical implementation of the circuit is done on a two-
ounce four-layer printed circuit board. The two internal layers
only the core regulator efficiency, use Figure 7. The core
regulator design of the HIP6020 is identical to that of the
HIP6021.
are dedicated for ground and power planes. The layout is
compact and several additional footprints are provided for
92
VCC_CORE = 2.0V
increased evaluation flexibility. The component side of the
board contains two embedded serpentine resistors. One in
series with the drain of Q4 and Q5, approximately 220m Ω
and 200m Ω respectively. These resistors is not necessary
for the proper operation of the circuit; their role is simply to
share the power dissipation which otherwise would be
dissipated entirely by Q4 or Q5. Both serpentine resistors
can be removed by shorted them via two separate footprints
on the bottom of the EVAL boards. Contact Intersil for board
layout Gerber files.
90
88
86
84
VCC_VDDQ = 1.5V
Power MOSFETs
The power transistors utilized by HIP6020/21EVAL1 belong
to Intersil’ newest line of 30V UltraFET MOSFETs. Featuring
82
0 10 20 30 40 50
COMBINED SWITCHING CONVERTERS OUTPUT POWER [W]
reduced r DS(ON) and low t rr and Q rr , these transistors allow
for elimination of the traditional lower MOSFET anti-parallel
schottky.
HIP6020/21EVAL1 Performance
Efficiency
Figure 7 displays the efficiency of the HIP6021EVAL1 core
regulator reference design versus load current. Laboratory
measurements were made with a 5V input and 100 linear
feet per minute (LFM) of airflow across the evaluation board.
The linear regulators are neglected since their efficiency is
not a figure of merit for the application circuit.
FIGURE 8. HIP6021EVAL1 MEASURED CONVERTER
EFFICIENCY
Load Transient Response
HIP6020EVAL1 response of the core voltage regulation to a
13.5A output step load transient is shown in Figure 9. An
Intel Slot 1 Test Tool provided the load transient which was
larger than the 9.5A design point. All other outputs are
subjected to the maximum transient loading conditions and
nominal output voltage settings as described in Table 1.
100
50
93
91
89
87
85
VCC_CORE = 2.0V
VCC_CORE
0
50
VCC_VDDQ
0
20
VCC_VTT
0
20
VCC_MCH
0
0
200
800
1200
1600
2000
83
0
4
8
12
16
20
TIME ( μ s)
SWITCHING CONVERTER OUTPUT CURRENT (A)
FIGURE 7. HIP6021EVAL1 MEASURED CONVERTER
EFFICIENCY
Similarly, Figure 8 displays the efficiency obtained in the
HIP6020EVAL1 reference design. Since this evaluation
platform contains two switching regulators, both switching
regulator outputs were simultaneously loaded and
measured. The efficiency curve in Figure 8 represents a
composite result of the overall circuit efficiency plotted
against total converter output power. For those interested in
4
FIGURE 9. HIP6020EVAL1 OUTPUT TRANSIENT RESPONSE
HIP6020/21EVAL1 Modifications
Input Capacitors Selection
In a DC/DC converter employing an input inductor, the input
RMS current is supplied entirely by the input capacitors. The
number of input capacitors is usually determined by their
maximum RMS current rating. The voltage rating at
maximum ambient temperature of the input capacitors
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